📚 End of Unit 3: Exam-style Case Study Questions | 单元3结束：考试风格案例研究题
This revision article focuses on Unit 3 Hardware for Cambridge A Level Computer Science. It presents exam-style case study questions that test logic circuits, processor architecture, memory, input/output and assembly language. Use the paired English-Chinese explanations to strengthen both technical vocabulary and exam technique.
本文复习剑桥A Level计算机科学第3单元“硬件”。通过考试风格的案例研究题，考查逻辑电路、处理器结构、存储器、输入/输出和汇编语言。使用中英对照讲解来巩固技术术语和答题技巧。
1. Case Study Scenario: Automated Greenhouse Monitor | 案例场景：温室自动监控器
A common Unit 3 exam style gives a real-world control system. In our case study, a greenhouse monitor reads temperature, soil moisture and light level from sensors. It must switch on a heater when temperature is low, a valve when soil is dry, and a lamp when light is dim. The processor receives digital signals after analogue-to-digital conversion.
常见的第3单元考试题会给出一个实际控制系统。本案例中，温室监控器读取温度、土壤湿度和光照传感器。当温度过低时启动加热器，土壤干燥时打开阀门，光照不足时开灯。处理器在模数转换后接收数字信号。
2. Logic Gates and Truth Tables | 逻辑门与真值表
Exam questions often ask you to complete a truth table for a given logic circuit or to design a circuit from a worded condition. For the greenhouse, let H = 1 when temperature is below 10 °C, W = 1 when soil moisture is below 30%, and L = 1 when light is below 200 lux. The heater should switch on when H = 1 AND W = 0, because wet soil may not need heating. The valve should open when W = 1 OR (H = 1 AND L = 0). Boolean expression: Heater = H · W’. Valve = W + H · L’.
考试题常要求你完成给定逻辑电路的真值表，或根据文字条件设计电路。在温室中，设 H = 1 表示温度低于 10 °C，W = 1 表示土壤湿度低于 30%，L = 1 表示光照低于 200 lux。当 H=1 且 W=0 时加热器启动，因为土壤湿润时可能不需要加热。阀门在 W=1 或（H=1 且 L=0）时打开。布尔表达式：Heater = H · W’，Valve = W + H · L’。
3. Simplifying Boolean Expressions | 简化布尔表达式
A 3-mark question might ask you to simplify F = A·B + A·B’. Using the identity X + X’ = 1, F = A·(B + B’) = A. Another common simplification uses De Morgan’s laws: (A + B)’ = A’·B’ and (A·B)’ = A’ + B’. You should show each step and name the law used.
三道小题可能会要求化简 F = A·B + A·B’。利用恒等式 X + X’ = 1，可得 F = A·(B + B’) = A。另一种常见化简使用德摩根定律：(A + B)’ = A’·B’ 以及 (A·B)’ = A’ + B’。你需要写出每一步并标明所用定律。
4. Combinational Logic: Half and Full Adders | 组合逻辑：半加器与全加器
A case study question may ask you to draw the truth table for a half adder. A half adder has inputs A and B, outputs Sum = A ⊕ B and Carry = A · B. A full adder has an additional carry-in Cᵢₙ. Sum = A ⊕ B ⊕ Cᵢₙ, Carry-out = A·B + Cᵢₙ·(A ⊕ B). These circuits are the building blocks of the Arithmetic Logic Unit.
案例题可能要求你画出半加器的真值表。半加器输入为 A 和 B，输出 Sum = A ⊕ B，Carry = A · B。全加器多一个进位输入 Cᵢₙ。Sum = A ⊕ B ⊕ Cᵢₙ，Carry-out = A·B + Cᵢₙ·(A ⊕ B)。这些电路是算术逻辑单元的构建模块。
5. Sequential Logic: Flip-flops and Registers | 时序逻辑：触发器与寄存器
Sequential logic has memory, so output depends on previous state. The SR flip-flop has Set and Reset: S=1, R=0 sets Q to 1; S=0, R=1 resets Q to 0; S=0, R=0 holds state; S=1, R=1 is invalid. A D flip-flop copies D to Q on the clock edge. Registers are groups of flip-flops used in the processor to store a word of data.
时序逻辑有记忆功能，输出取决于之前的状态。SR触发器有置位和复位：S=1、R=0 将 Q 置 1；S=0、R=1 将 Q 复位为 0；S=0、R=0 保持状态；S=1、R=1 是无效状态。D触发器在时钟边沿将 D 复制到 Q。寄存器是触发器的组合，用于处理器中存储一个字的数据。
6. Processor Components and Buses | 处理器组件与总线
Case studies often label a diagram of the processor. Key components: Control Unit (CU) decodes instructions and sends control signals; Arithmetic Logic Unit (ALU) performs arithmetic and logic operations; registers such as PC, MAR, MDR, CIR and accumulator hold data temporarily. The three buses are address bus (one-way), data bus (bidirectional) and control bus (bidirectional).
案例题经常要求标注处理器结构图。关键部件：控制单元（CU）译码指令并发送控制信号；算术逻辑单元（ALU）执行算术和逻辑运算；寄存器如 PC、MAR、MDR、CIR 和累加器暂存数据。三条总线是地址总线（单向）、数据总线（双向）和控制总线（双向）。
7. The Fetch-Decode-Execute Cycle | 取指-解码-执行周期
You must be able to trace register contents during the cycle. Fetch: PC → MAR, address placed on address bus, memory returns instruction to MDR, MDR → CIR, PC incremented. Decode: CU interprets opcode. Execute: CU sends signals, ALU performs operation or data is transferred. Exam questions may give initial values and ask for values after one cycle.
你必须能跟踪周期中的寄存器内容。取指：PC → MAR，地址放到地址总线，存储器将指令返回 MDR，MDR → CIR，PC 自增。译码：CU 解释操作码。执行：CU 发送控制信号，ALU 执行运算或数据传送。考试题可能给出初值，要求一个周期后的寄存器值。
8. Memory Hierarchy and Cache | 存储器层次结构与缓存
Memory hierarchy balances speed and cost. Registers are fastest, then cache, RAM, and secondary storage. Cache stores frequently used instructions and data, reducing average access time. Virtual memory extends RAM using disk space, but thrashing can occur if pages are swapped too often. Addressable memory size depends on address bus width: n bits address 2ⁿ locations.
存储器层次结构平衡速度和成本。寄存器最快，其次是缓存、RAM 和辅助存储器。缓存存储常用指令和数据，降低平均访问时间。虚拟内存用磁盘空间扩展 RAM，但如果页面频繁换入换出会发生抖动。可寻址存储器大小取决于地址总线宽度：n 位可以寻址 2ⁿ 个存储单元。
9. Input/Output and Interrupts | 输入/输出与中断
The greenhouse uses sensors through an ADC. Data transfer can be polled or interrupt-driven. With interrupts, the I/O device sends a signal to the processor, the current instruction finishes, registers are saved, an Interrupt Service Routine runs, then registers are restored. DMA allows fast transfer of blocks of data directly between device and memory without CPU involvement.
温室通过模数转换器使用传感器。数据传送可以是轮询或中断驱动。使用中断时，I/O设备向处理器发送信号，当前指令结束，保存寄存器，执行中断服务程序，然后恢复寄存器。DMA允许数据块在设备和存储器之间直接快速传送，无需CPU介入。
10. Assembly Language and Addressing Modes | 汇编语言与寻址模式
Exam-style questions often give assembly code such as LDR R1, #5 or ADD R0, R1, R2. Immediate addressing uses the operand itself. Direct addressing gives a memory address. Indirect addressing gives a location that contains the address of the operand. Relative addressing adds an offset to the PC. The opcode tells the CU what to do; the operand gives the data or address.
考试题常给出汇编代码，如 LDR R1, #5 或 ADD R0, R1, R2。立即寻址使用操作数本身。直接寻址给出内存地址。间接寻址给出的位置包含操作数的地址。相对寻址将偏移量加到 PC。操作码告诉 CU 做什么；操作数给出数据或地址。
11. RISC vs CISC and Parallel Processing | RISC与CISC及并行处理
RISC processors use a small set of simple instructions, often one clock cycle each, relying on compiler optimisation. CISC processors have complex instructions that may take multiple cycles. Pipelining overlaps fetch, decode and execute of different instructions. Parallel processing uses multiple cores or processors; SIMD applies one instruction to many data items, MIMD runs different instructions on different data.
RISC处理器使用少量简单指令，通常每条一个时钟周期，依赖编译器优化。CISC处理器有复杂指令，可能占用多个周期。流水线重叠不同指令的取指、译码和执行。并行处理使用多个核心或处理器；SIMD对多个数据项使用一条指令，MIMD对不同的数据运行不同指令。
12. Exam-style Mark Scheme Tips | 考试风格评分方案提示
In case study questions, use technical terms precisely: ‘address bus carries memory addresses’, not ‘data’. Show all Boolean simplification steps. In trace tables, list each register change in order. For 6-mark explain questions, write 3 distinct points with development. If asked to design a circuit, draw it neatly and label inputs and outputs. Manage time: spend 1.5 minutes per mark.
在案例研究题中，准确使用术语：“地址总线传送存储器地址”，而不是“数据”。展示布尔化简的每一步。在跟踪表中，按顺序列出每个寄存器变化。对于6分解释题，写3个不同要点并展开。如果要求设计电路，绘图要整洁并标注输入输出。管理时间：每分花1.5分钟。
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